1. Field
Example embodiments relate to a semiconductor package and a method of manufacturing the semiconductor package. More particularly, example embodiments relate to a semiconductor package including at least two semiconductor chips stacked on each other and a method of manufacturing the semiconductor package.
2. Description of the Related Art
Semiconductor packages are becoming miniaturized and lightweight according to the miniaturization trend of electronic products using semiconductor devices. For example, in order to minimize a mounting area, a stack package including at least two unit semiconductor chips stacked on a wafer level has been researched.
In the wafer level package, the stacked semiconductor chips may include a through electrode or plug that penetrates the semiconductor chip. A connection member such as a metal bump may be disposed on the through electrode to electrically connect the semiconductor chips to each other. The through electrode called through-silicon via (TSV) can be used for the wafer level package. For example, the through electrode may be formed using copper (Cu) having a low resistance.
Conventionally, after the through electrode is formed in a semiconductor such as a wafer, a backside of the substrate may be planarized until an end portion of the through electrode is exposed through the backside of the substrate. By performing the planarization process, the thickness of the substrate may be decreased. Accordingly, a high-cost wafer supporting system (WSS) may be required to handle the thin wafer for following processes. Further, the through electrodes may be damaged by the planarization process.